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EP1810LC-20 Tech Specifications

Category Embedded - FPGAs (Field Programmable Gate Array)
Manufacturer ALTERA
Surface Mount YES
Number of Terminals 68Terminals
Package Description QCCJ, LDCC68,1.0SQ
Package Style CHIP CARRIER
Package Body Material PLASTIC/EPOXY
Package Equivalence Code LDCC68,1.0SQ
Supply Voltage-Nom 5 V
Reflow Temperature-Max (s) NOT SPECIFIED
Supply Voltage-Min 4.75 V
Operating Temperature-Max 70 °C
Rohs Code No
Manufacturer Part Number EP1810LC-20
Clock Frequency-Max 50 MHz
Package Code QCCJ
Package Shape SQUARE
Manufacturer Altera Corporation
Part Life Cycle Code Obsolete
Number of I/O Lines 48I/O Lines
Ihs Manufacturer ALTERA CORP
Supply Voltage-Max 5.25 V
Risk Rank 5.75
Part Package Code LCC
JESD-609 Code e0
Pbfree Code No
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Additional Feature MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal Form J BEND
Peak Reflow Temperature (Cel) NOT SPECIFIED
Terminal Pitch 1.27 mm
Reach Compliance Code compliant
Pin Count 68
JESD-30 Code S-PQCC-J68
Qualification Status Not Qualified
Power Supplies 5 V
Temperature Grade COMMERCIAL
Propagation Delay 22 ns
Organization 12 DEDICATED INPUTS, 48 I/O
Programmable Logic Type OT PLD
Output Function MACROCELL
Number of Macro Cells 48Macro Cells
JTAG BST NO
Number of Dedicated Inputs 12Dedicated Inputs
In-System Programmable NO
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