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EP610DC-35 Tech Specifications

Category Embedded - PLDs (Programmable Logic Device)
Manufacturer ALTERA
Surface Mount NO
Number of Terminals 24Terminals
Package Description WINDOWED, CERDIP-24
Package Style IN-LINE
Package Body Material CERAMIC, GLASS-SEALED
Package Equivalence Code DIP24,.3
Supply Voltage-Nom 5 V
Reflow Temperature-Max (s) NOT SPECIFIED
Supply Voltage-Min 4.75 V
Operating Temperature-Max 70 °C
Rohs Code No
Manufacturer Part Number EP610DC-35
Clock Frequency-Max 28.6 MHz
Package Code DIP
Package Shape RECTANGULAR
Manufacturer Altera Corporation
Part Life Cycle Code Obsolete
Number of I/O Lines 16I/O Lines
Ihs Manufacturer ALTERA CORP
Supply Voltage-Max 5.25 V
Risk Rank 8.38
Part Package Code DIP
JESD-609 Code e0
Pbfree Code No
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Additional Feature MACROCELLS INTERCONNECTED BY GLOBAL BUS; 16 MACROCELLS; 2 EXTERNAL CLOCKS
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position DUAL
Terminal Form THROUGH-HOLE
Peak Reflow Temperature (Cel) NOT SPECIFIED
Terminal Pitch 2.54 mm
Reach Compliance Code unknown
Pin Count 24
JESD-30 Code R-GDIP-T24
Number of Outputs 16Outputs
Qualification Status Not Qualified
Power Supplies 5 V
Temperature Grade COMMERCIAL
Propagation Delay 37 ns
Architecture PAL-TYPE
Number of Inputs 20Inputs
Organization 4 DEDICATED INPUTS, 16 I/O
Programmable Logic Type UV PLD
Output Function MACROCELL
Number of Dedicated Inputs 4Dedicated Inputs
Number of Product Terms 160Product Terms
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