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EPM5032PC-25 Tech Specifications

Category Embedded - CPLDs (Complex Programmable Logic Devices)
Manufacturer ALTERA
Surface Mount NO
Number of Terminals 28Terminals
Package Description DIP, DIP28,.3
Package Style IN-LINE
Package Body Material PLASTIC/EPOXY
Package Equivalence Code DIP28,.3
Supply Voltage-Nom 5 V
Reflow Temperature-Max (s) 30
Supply Voltage-Min 4.75 V
Operating Temperature-Max 70 °C
Rohs Code No
Manufacturer Part Number EPM5032PC-25
Clock Frequency-Max 50 MHz
Package Code DIP
Package Shape RECTANGULAR
Manufacturer Altera Corporation
Part Life Cycle Code Obsolete
Number of I/O Lines 16I/O Lines
Ihs Manufacturer ALTERA CORP
Supply Voltage-Max 5.25 V
Risk Rank 7.99
Part Package Code DIP
JESD-609 Code e0
Pbfree Code No
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Additional Feature MACROCELLS INTERCONNECTED BY PIA; 1 LAB; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position DUAL
Terminal Form THROUGH-HOLE
Peak Reflow Temperature (Cel) 220
Terminal Pitch 2.54 mm
Reach Compliance Code unknown
Pin Count 28
JESD-30 Code R-PDIP-T28
Number of Outputs 16Outputs
Qualification Status Not Qualified
Power Supplies 5 V
Temperature Grade COMMERCIAL
Propagation Delay 25 ns
Architecture PAL-TYPE
Number of Inputs 24Inputs
Organization 7 DEDICATED INPUTS, 16 I/O
Programmable Logic Type OT PLD
Output Function MACROCELL
Number of Dedicated Inputs 7Dedicated Inputs
Number of Product Terms 320Product Terms
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