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- EPM7064AETI44-7
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EPM7064AETI44-7 Tech Specifications
| Category | Embedded - CPLDs (Complex Programmable Logic Devices) | |
| Manufacturer | ALTERA | |
| Mounting Type | Surface Mount | |
| Package / Case | 44-TQFP | |
| Surface Mount | YES | |
| Supplier Device Package | 44-TQFP (10x10) | |
| Number of Terminals | 44Terminals | |
| Number of I/Os | 36I/Os | |
| Number of Macrocells | 64Macrocells | |
| Package Description | LQFP, TQFP44,.47SQ,32 | |
| Package Style | FLATPACK, LOW PROFILE | |
| Moisture Sensitivity Levels | 3 | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Equivalence Code | TQFP44,.47SQ,32 | |
| Operating Temperature-Min | -40 °C | |
| Supply Voltage-Nom | 3.3 V | |
| Reflow Temperature-Max (s) | 30 | |
| Supply Voltage-Min | 3 V | |
| Operating Temperature-Max | 85 °C | |
| Rohs Code | No | |
| Manufacturer Part Number | EPM7064AETI44-7 | |
| Clock Frequency-Max | 135.1 MHz | |
| Package Code | LQFP | |
| Package Shape | SQUARE | |
| Manufacturer | Intel Corporation | |
| Part Life Cycle Code | Active | |
| Number of I/O Lines | 36I/O Lines | |
| Samacsys Description | CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 64 Macro 36 IOs | |
| Ihs Manufacturer | INTEL CORP | |
| Supply Voltage-Max | 3.6 V | |
| Risk Rank | 1.63 | |
| Operating Temperature | -40°C ~ 85°C (TA) | |
| Series | MAX® 7000A | |
| Packaging | Tray | |
| JESD-609 Code | e0 |
| Part Status | Active | |
| ECCN Code | EAR99 | |
| Terminal Finish | Tin/Lead (Sn/Pb) | |
| HTS Code | 8542.39.00.01 | |
| Subcategory | Programmable Logic Devices | |
| Technology | CMOS | |
| Terminal Position | QUAD | |
| Terminal Form | GULL WING | |
| Peak Reflow Temperature (Cel) | 235 | |
| Terminal Pitch | 0.8 mm | |
| Reach Compliance Code | compliant | |
| Base Part Number | EPM7064 | |
| JESD-30 Code | S-PQFP-G44 | |
| Number of Outputs | 36Outputs | |
| Qualification Status | Not Qualified | |
| Power Supplies | 2.5/3.3,3.3 V | |
| Temperature Grade | INDUSTRIAL | |
| Programmable Type | In System Programmable | |
| Propagation Delay | 7.5 ns | |
| Architecture | PLA-TYPE | |
| Number of Inputs | 36Inputs | |
| Organization | 0 DEDICATED INPUTS, 36 I/O | |
| Seated Height-Max | 1.27 mm | |
| Programmable Logic Type | EE PLD | |
| Number of Gates | 1250Gates | |
| Output Function | MACROCELL | |
| Number of Macro Cells | 64Macro Cells | |
| JTAG BST | YES | |
| Voltage Supply - Internal | 3 V ~ 3.6 V | |
| Delay Time tpd(1) Max | 7.5ns | |
| Number of Logic Elements/Blocks | 4Logic Elements/Blocks | |
| In-System Programmable | YES | |
| Number of Product Terms | 2048Product Terms | |
| Width | 10 mm | |
| Length | 10 mm |
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