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- EPM7192SQC160-10
ALTERA EPM7192SQC160-10 CPLDs
192Macro Cells
IN STOCK
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Mult. : 1
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EPM7192SQC160-10 Tech Specifications
| Category | Embedded - CPLDs (Complex Programmable Logic Devices) | |
| Manufacturer | ALTERA | |
| Mounting Type | Surface Mount | |
| Package / Case | 160-BQFP | |
| Surface Mount | YES | |
| Supplier Device Package | 160-PQFP (28x28) | |
| Number of Terminals | 160Terminals | |
| Number of I/Os | 124I/Os | |
| Number of Macrocells | 192Macrocells | |
| Package Description | PLASTIC, QFP-160 | |
| Package Style | FLATPACK | |
| Moisture Sensitivity Levels | 3 | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Equivalence Code | QFP160,1.2SQ | |
| Supply Voltage-Nom | 5 V | |
| Reflow Temperature-Max (s) | 30 | |
| Supply Voltage-Min | 4.75 V | |
| Operating Temperature-Max | 70 °C | |
| Rohs Code | No | |
| Manufacturer Part Number | EPM7192SQC160-10 | |
| Clock Frequency-Max | 125 MHz | |
| Package Code | QFP | |
| Package Shape | SQUARE | |
| Manufacturer | Altera Corporation | |
| Part Life Cycle Code | Transferred | |
| Number of I/O Lines | 124I/O Lines | |
| Ihs Manufacturer | ALTERA CORP | |
| Supply Voltage-Max | 5.25 V | |
| Risk Rank | 3.87 | |
| Part Package Code | QFP | |
| Operating Temperature | 0°C ~ 70°C (TA) | |
| Series | MAX® 7000S | |
| Packaging | Tray | |
| JESD-609 Code | e0 |
| Pbfree Code | No | |
| Part Status | Obsolete | |
| Terminal Finish | Tin/Lead (Sn/Pb) | |
| Additional Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V | |
| HTS Code | 8542.39.00.01 | |
| Subcategory | Programmable Logic Devices | |
| Technology | CMOS | |
| Terminal Position | QUAD | |
| Terminal Form | GULL WING | |
| Peak Reflow Temperature (Cel) | 220 | |
| Terminal Pitch | 0.65 mm | |
| Reach Compliance Code | unknown | |
| Base Part Number | EPM7192 | |
| Pin Count | 160 | |
| JESD-30 Code | S-PQFP-G160 | |
| Qualification Status | Not Qualified | |
| Power Supplies | 3.3/5,5 V | |
| Temperature Grade | COMMERCIAL | |
| Programmable Type | In System Programmable | |
| Propagation Delay | 10 ns | |
| Organization | 0 DEDICATED INPUTS, 124 I/O | |
| Seated Height-Max | 4.07 mm | |
| Programmable Logic Type | EE PLD | |
| Number of Gates | 3750Gates | |
| Output Function | MACROCELL | |
| Number of Macro Cells | 192Macro Cells | |
| JTAG BST | YES | |
| Voltage Supply - Internal | 4.75 V ~ 5.25 V | |
| Delay Time tpd(1) Max | 10.0ns | |
| Number of Logic Elements/Blocks | 12Logic Elements/Blocks | |
| In-System Programmable | YES | |
| Width | 28 mm | |
| Length | 28 mm |
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