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- EPXA1F484C2
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EPXA1F484C2 Tech Specifications
| Category | Embedded - FPGAs (Field Programmable Gate Array) with Microcontrollers | |
| Manufacturer | ALTERA | |
| Mounting Type | Surface Mount | |
| Package / Case | 484-BBGA | |
| Mount | Surface Mount | |
| Surface Mount | YES | |
| Number of Pins | 484Pins | |
| Supplier Device Package | 484-FBGA (23x23) | |
| Number of Terminals | 484Terminals | |
| Manufacturer Part Number | PDG34MH400E4ML | |
| Approvals | CE, CSA, UL | |
| Manufacturer | Cutler Hammer, Div of Eaton Corp | |
| Mounting | Panel | |
| RoHS | Compliant | |
| Package | Tray | |
| Mfr | Altera | |
| Product Status | Obsolete | |
| Package Description | BGA, | |
| Package Style | GRID ARRAY | |
| Moisture Sensitivity Levels | 3 | |
| Package Body Material | PLASTIC/EPOXY | |
| Supply Voltage-Nom | 1.8 V | |
| Reflow Temperature-Max (s) | 30 | |
| Supply Voltage-Min | 1.71 V | |
| Operating Temperature-Max | 85 °C | |
| Rohs Code | No | |
| Package Code | BGA | |
| Package Shape | SQUARE | |
| Part Life Cycle Code | Active | |
| Number of I/O Lines | 186I/O Lines | |
| Ihs Manufacturer | ROCHESTER ELECTRONICS INC | |
| Supply Voltage-Max | 1.89 V | |
| Risk Rank | 5.85 | |
| Part Package Code | BGA | |
| Operating Temperature | 0°C ~ 85°C |
| Series | Excalibur™ | |
| Packaging | Tray | |
| JESD-609 Code | e0 | |
| Pbfree Code | No | |
| Part Status | Obsolete | |
| Terminal Finish | TIN LEAD | |
| Max Operating Temperature | 85 °C | |
| Min Operating Temperature | 0 °C | |
| Voltage - Supply | 1.8V | |
| Terminal Position | BOTTOM | |
| Terminal Form | BALL | |
| Peak Reflow Temperature (Cel) | 220 | |
| Terminal Pitch | 1 mm | |
| Reach Compliance Code | unknown | |
| Current Rating | 400 A | |
| Frequency | 200 MHz | |
| Pin Count | 484 | |
| JESD-30 Code | S-PBGA-B484 | |
| Qualification Status | COMMERCIAL | |
| Temperature Grade | OTHER | |
| Interface | EBI/EMI, UART/USART | |
| Speed | 200MHz | |
| Organization | 0 DEDICATED INPUTS, 186 I/O | |
| Seated Height-Max | 2.1 mm | |
| Programmable Logic Type | LOADABLE PLD | |
| EEPROM Size | -- | |
| Output Function | MACROCELL | |
| Core Type | 32-Bit ARM9 | |
| Data SRAM Bytes | 16K | |
| FPGA Gates | 100K | |
| Program SRAM Bytes | 32K | |
| FPGA Core Cells | 4160 | |
| FPGA SRAM | -- | |
| Width | 23 mm | |
| Length | 23 mm |
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