Altera Corporation EPM5128LC68-2 Programmable Logic Devices
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EPM5128LC68-2 Tech Specifications
| Category | Embedded - PLDs (Programmable Logic Device) | |
| Manufacturer | ALTERA | |
| Surface Mount | YES | |
| Number of Terminals | 68Terminals | |
| Rohs Code | No | |
| Part Life Cycle Code | Transferred | |
| Ihs Manufacturer | ALTERA CORP | |
| Part Package Code | LCC | |
| Package Description | QCCJ, LDCC68,1.0SQ | |
| Clock Frequency-Max | 40 MHz | |
| Number of I/O Lines | 52I/O Lines | |
| Operating Temperature-Max | 70 °C | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | QCCJ | |
| Package Equivalence Code | LDCC68,1.0SQ | |
| Package Shape | SQUARE | |
| Package Style | CHIP CARRIER | |
| Supply Voltage-Max | 5.25 V | |
| Supply Voltage-Min | 4.75 V | |
| Supply Voltage-Nom | 5 V | |
| JESD-609 Code | e0 | |
| Terminal Finish | TIN LEAD |
| Additional Feature | 128 MACROCELLS; SHARED INPUT/CLOCK; SHARED PRODUCT TERMS | |
| HTS Code | 8542.39.00.01 | |
| Terminal Position | QUAD | |
| Terminal Form | J BEND | |
| Peak Reflow Temperature (Cel) | 220 | |
| Terminal Pitch | 1.27 mm | |
| Reach Compliance Code | unknown | |
| Pin Count | 68 | |
| JESD-30 Code | S-PQCC-J68 | |
| Qualification Status | Not Qualified | |
| Temperature Grade | COMMERCIAL | |
| Propagation Delay | 45 ns | |
| Organization | 7 DEDICATED INPUTS, 52 I/O | |
| Seated Height-Max | 5.08 mm | |
| Programmable Logic Type | OT PLD | |
| Output Function | MACROCELL | |
| Number of Macro Cells | 128Macro Cells | |
| JTAG BST | NO | |
| Number of Dedicated Inputs | 7Dedicated Inputs | |
| In-System Programmable | NO | |
| Length | 24.23 mm | |
| Width | 24.23 mm |
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EPM5128LC68-2 Documents
Download datasheets and manufacturer documentation for EPM5128LC68-2
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