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EPM5130GC100 Tech Specifications

Category Embedded - PLDs (Programmable Logic Device)
Manufacturer ALTERA
Surface Mount NO
Number of Terminals 100Terminals
Rohs Code No
Part Life Cycle Code Transferred
Ihs Manufacturer ALTERA CORP
Part Package Code PGA
Package Description WPGA, PGA100M,13X13
Clock Frequency-Max 33.3 MHz
Moisture Sensitivity Levels 1
Number of I/O Lines 64I/O Lines
Operating Temperature-Max 70 °C
Package Body Material CERAMIC, METAL-SEALED COFIRED
Package Code WPGA
Package Equivalence Code PGA100M,13X13
Package Shape SQUARE
Package Style GRID ARRAY, WINDOW
Supply Voltage-Max 5.25 V
Supply Voltage-Min 4.75 V
Supply Voltage-Nom 5 V
JESD-609 Code e0
Terminal Finish TIN LEAD
Additional Feature 128 MACROCELLS; SHARED INPUT/CLOCK; SHARED PRODUCT TERMS
HTS Code 8542.39.00.01
Terminal Position PERPENDICULAR
Terminal Form PIN/PEG
Peak Reflow Temperature (Cel) 220
Terminal Pitch 2.54 mm
Reach Compliance Code unknown
Pin Count 100
JESD-30 Code S-CPGA-P100
Qualification Status Not Qualified
Temperature Grade COMMERCIAL
Propagation Delay 55 ns
Organization 19 DEDICATED INPUTS, 64 I/O
Seated Height-Max 4.96 mm
Programmable Logic Type UV PLD
Output Function MACROCELL
Number of Macro Cells 128Macro Cells
JTAG BST NO
Number of Dedicated Inputs 19Dedicated Inputs
In-System Programmable NO
Length 33.528 mm
Width 33.528 mm
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EPM5130GC100 Documents

Download datasheets and manufacturer documentation for   EPM5130GC100

  • Datasheets
EPM5130GC100 brand manufacturers: Altera Corporation, Elecinsight stock, EPM5130GC100 reference price.Altera Corporation. EPM5130GC100 parameters, EPM5130GC100 Datasheet PDF and pin diagram description download.You can use the EPM5130GC100 Embedded - PLDs (Programmable Logic Device), DSP Datesheet PDF, find EPM5130GC100 pin diagram and circuit diagram and usage method of function,EPM5130GC100 electronics tutorials.You can download from the Elecinsight.