Altera Corporation EPM5130LC-2 Programmable Logic Devices
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EPM5130LC-2 Tech Specifications
| Category | Embedded - PLDs (Programmable Logic Device) | |
| Manufacturer | ALTERA | |
| Surface Mount | YES | |
| Number of Terminals | 84Terminals | |
| Supply Voltage-Nom | 5 V | |
| Supply Voltage-Min | 4.75 V | |
| Supply Voltage-Max | 5.25 V | |
| Package Style | CHIP CARRIER | |
| Package Shape | SQUARE | |
| Package Equivalence Code | LDCC84,1.2SQ | |
| Package Code | QCCJ | |
| Package Body Material | PLASTIC/EPOXY | |
| Operating Temperature-Max | 70 °C | |
| Number of I/O Lines | 48I/O Lines | |
| Clock Frequency-Max | 40 MHz | |
| Package Description | QCCJ, LDCC84,1.2SQ | |
| Part Package Code | LCC | |
| Ihs Manufacturer | ALTERA CORP | |
| Part Life Cycle Code | Obsolete | |
| Rohs Code | No | |
| JESD-609 Code | e0 |
| Terminal Finish | TIN LEAD | |
| Additional Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK | |
| HTS Code | 8542.39.00.01 | |
| Terminal Position | QUAD | |
| Terminal Form | J BEND | |
| Peak Reflow Temperature (Cel) | 220 | |
| Terminal Pitch | 1.27 mm | |
| Reach Compliance Code | unknown | |
| Pin Count | 84 | |
| JESD-30 Code | S-PQCC-J84 | |
| Qualification Status | Not Qualified | |
| Temperature Grade | COMMERCIAL | |
| Propagation Delay | 45 ns | |
| Organization | 19 DEDICATED INPUTS, 48 I/O | |
| Programmable Logic Type | OT PLD | |
| Output Function | MACROCELL | |
| Number of Macro Cells | 128Macro Cells | |
| JTAG BST | NO | |
| Number of Dedicated Inputs | 19Dedicated Inputs | |
| In-System Programmable | NO |
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EPM5130LC-2 Documents
Download datasheets and manufacturer documentation for EPM5130LC-2
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