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- 74AUP1G00SE-7
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74AUP1G00SE-7 Tech Specifications
| Category | Logic - Gates and Inverters | |
| Manufacturer | Diodes | |
| Contact Plating | Tin | |
| Mount | Surface Mount | |
| Mounting Type | Surface Mount | |
| Package / Case | 5-TSSOP, SC-70-5, SOT-353 | |
| Number of Pins | 5Pins | |
| Logic Level-High | 1.6V ~ 2V | |
| Logic Level-Low | 0.7V ~ 0.9V | |
| Operating Temperature | -40°C~125°C | |
| Packaging | Cut Tape (CT) | |
| Series | 74AUP | |
| JESD-609 Code | e3 | |
| Pbfree Code | yes | |
| Part Status | Discontinued | |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) | |
| Number of Terminations | 5Terminations | |
| Packing Method | TAPE AND REEL | |
| Voltage - Supply | 0.8V~3.6V | |
| Terminal Position | DUAL | |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 | |
| Number of Functions | 1Function | |
| Supply Voltage | 3V | |
| Time@Peak Reflow Temperature-Max (s) | 40 | |
| Pin Count | 5 | |
| Number of Outputs | 1Output | |
| Supply Voltage-Max (Vsup) | 3.6V | |
| Supply Voltage-Min (Vsup) | 0.8V | |
| Load Capacitance | 30pF | |
| Propagation Delay | 6.5 ns | |
| Quiescent Current | 500nA | |
| Family | AUP/ULP/V | |
| Logic Function | NAND | |
| Number of Inputs | 2Inputs | |
| Logic Type | NAND Gate | |
| Max Propagation Delay @ V, Max CL | 6.5ns @ 3.3V, 30pF | |
| Schmitt Trigger | NO | |
| REACH SVHC | No SVHC | |
| Radiation Hardening | No | |
| RoHS Status | ROHS3 Compliant |
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74AUP1G00SE-7 Documents
Download datasheets and manufacturer documentation for 74AUP1G00SE-7
- Environmental InformationDiodes RoHS 3 Cert
- RohsStatementDiodes-Inc.-74AUP1G00SE-7.pdf
- Datasheets74AUP1G00 74AUP1G00SE-7-Diodes-Inc.-datasheet-17556904.pdf
- PCN Assembly/OriginMult Dev Assembly Site Add 29/Aug/2017
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