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- 74AUP1G09FS3-7
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74AUP1G09FS3-7 Tech Specifications
| Category | Logic - Gates and Inverters | |
| Manufacturer | Diodes | |
| Factory Lead Time | 18 Weeks | |
| Mount | Surface Mount | |
| Mounting Type | Surface Mount | |
| Package / Case | 4-XFDFN Exposed Pad | |
| Logic Level-High | 1.6V ~ 2V | |
| Logic Level-Low | 0.7V ~ 0.9V | |
| Operating Temperature | -40°C~125°C | |
| Packaging | Tape & Reel (TR) | |
| Series | 74AUP | |
| Published | 2013 | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) | |
| Number of Terminations | 4Terminations | |
| Capacitance | 6pF | |
| Voltage - Supply | 0.8V~3.6V | |
| Terminal Position | DUAL | |
| Terminal Form | NO LEAD | |
| Peak Reflow Temperature (Cel) | 260 | |
| Number of Functions | 1Function | |
| Supply Voltage | 3V | |
| Terminal Pitch | 0.48mm |
| Time@Peak Reflow Temperature-Max (s) | 30 | |
| Pin Count | 4 | |
| JESD-30 Code | S-PDSO-N4 | |
| Qualification Status | Not Qualified | |
| Supply Voltage-Max (Vsup) | 3.6V | |
| Supply Voltage-Min (Vsup) | 0.8V | |
| Number of Circuits | 1Circuit | |
| Output Current | 20mA | |
| Propagation Delay | 12.7 ns | |
| Quiescent Current | 500nA | |
| Turn On Delay Time | 27 ns | |
| Family | AUP/ULP/V | |
| Logic Function | AND | |
| Number of Inputs | 2Inputs | |
| Logic Type | AND Gate | |
| Max Propagation Delay @ V, Max CL | 12.7ns @ 3.3V, 30pF | |
| Schmitt Trigger | YES | |
| Features | Open Drain | |
| Length | 0.8mm | |
| Height Seated (Max) | 0.35mm | |
| Width | 0.8mm | |
| RoHS Status | ROHS3 Compliant |
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74AUP1G09FS3-7 Documents
Download datasheets and manufacturer documentation for 74AUP1G09FS3-7
- Environmental InformationDiodes RoHS 3 Cert
- Datasheets74AUP1G09
- PCN Assembly/OriginMult Dev Assembly/Test Sit Add 1/Mar/2018
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