Integrated Device Technology (IDT) 7201LA50JG FIFOs Memory ICs
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7201LA50JG Tech Specifications
| Category | Logic - FIFOs Memory | |
| Manufacturer | IDT | |
| Surface Mount | YES | |
| Number of Terminals | 32Terminals | |
| Manufacturer Part Number | 7201LA50JG | |
| Rohs Code | Yes | |
| Part Life Cycle Code | Active | |
| Ihs Manufacturer | INTEGRATED DEVICE TECHNOLOGY INC | |
| Part Package Code | QFJ | |
| Package Description | QCCJ, LDCC32,.5X.6 | |
| Risk Rank | 5.15 | |
| Access Time-Max | 50 ns | |
| Clock Frequency-Max (fCLK) | 15 MHz | |
| Moisture Sensitivity Levels | 1 | |
| Number of Words | 512 wordsWord | |
| Number of Words Code | 512Words Codes | |
| Operating Temperature-Max | 70 °C | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | QCCJ | |
| Package Equivalence Code | LDCC32,.5X.6 | |
| Package Shape | RECTANGULAR | |
| Package Style | CHIP CARRIER | |
| Supply Voltage-Nom (Vsup) | 5 V | |
| Reflow Temperature-Max (s) | 30 | |
| JESD-609 Code | e3 | |
| Pbfree Code | Yes | |
| ECCN Code | EAR99 | |
| Terminal Finish | Matte Tin (Sn) - annealed |
| Additional Feature | RETRANSMIT | |
| HTS Code | 8542.32.00.71 | |
| Terminal Position | QUAD | |
| Terminal Form | J BEND | |
| Peak Reflow Temperature (Cel) | 260 | |
| Number of Functions | 1Function | |
| Terminal Pitch | 1.27 mm | |
| Reach Compliance Code | compliant | |
| Pin Count | 32 | |
| JESD-30 Code | R-PQCC-J32 | |
| Qualification Status | Not Qualified | |
| Supply Voltage-Max (Vsup) | 5.5 V | |
| Power Supplies | 5 V | |
| Temperature Grade | COMMERCIAL | |
| Supply Voltage-Min (Vsup) | 4.5 V | |
| Operating Mode | ASYNCHRONOUS | |
| Supply Current-Max | 0.08 mA | |
| Organization | 512X9 | |
| Seated Height-Max | 3.55 mm | |
| Memory Width | 9 | |
| Standby Current-Max | 0.005 A | |
| Memory Density | 4608 bit | |
| Parallel/Serial | PARALLEL | |
| Memory IC Type | OTHER FIFO | |
| Output Enable | NO | |
| Cycle Time | 65 ns | |
| Length | 13.97 mm | |
| Width | 11.43 mm |
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