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- EP2S30F672C3N
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EP2S30F672C3N Tech Specifications
| Category | Embedded - FPGAs (Field Programmable Gate Array) | |
| Manufacturer | Intel | |
| Factory Lead Time | 8 Weeks | |
| Mounting Type | Surface Mount | |
| Surface Mount | YES | |
| Package / Case | 672-BBGA, FCBGA | |
| Number of I/Os | 500I/Os | |
| Series | Stratix® II | |
| Operating Temperature | 0°C~85°C TJ | |
| Packaging | Tray | |
| JESD-609 Code | e1 | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | |
| Number of Terminations | 672Terminations | |
| ECCN Code | 3A001.A.7.A | |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) | |
| HTS Code | 8542.39.00.01 | |
| Voltage - Supply | 1.15V~1.25V | |
| Terminal Position | BOTTOM | |
| Terminal Form | BALL | |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 1.2V | |
| Terminal Pitch | 1.27mm | |
| Time@Peak Reflow Temperature-Max (s) | 40 | |
| Base Part Number | EP2S30 | |
| JESD-30 Code | S-PBGA-B672 | |
| Number of Outputs | 492Outputs | |
| Qualification Status | Not Qualified | |
| Power Supplies | 1.21.5/3.33.3V | |
| Clock Frequency | 717MHz | |
| Number of Inputs | 500Inputs | |
| Organization | 13552 CLBS | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Number of Logic Elements/Cells | 33880Logic Elements/Cells | |
| Total RAM Bits | 1369728 | |
| Number of LABs/CLBs | 1694LABs/CLBs | |
| Combinatorial Delay of a CLB-Max | 4.45 ns | |
| Number of CLBs | 13552CLBs | |
| Width | 35mm | |
| Length | 35mm | |
| Height Seated (Max) | 2.6mm | |
| RoHS Status | RoHS Compliant |
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EP2S30F672C3N Documents
Download datasheets and manufacturer documentation for EP2S30F672C3N
- DatasheetsStratix II Device Handbook, Volume1 Stratix II Device Handbook 672-FBGA Pkg Info Virtual JTAG Megafuntion User Guide
- PCN PackagingMult Dev Label CHG 24/Jan/2020 Mult Dev Dessicant Chg 19/Jul/2019 All Dev Pkg Chg 1/Aug/2018 Mult Dev Label Chgs 24/Feb/2020
- PCN OtherReadiness Plan 18/Jan/2019
- PCN Obsolescence/ EOLMult Dev Add Subs 6/Sep/2019
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