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DPLD610-25 Tech Specifications

Category Embedded - PLDs (Programmable Logic Device)
Manufacturer Intel
Surface Mount NO
Number of Terminals 24Terminals
Rohs Code No
Part Life Cycle Code Obsolete
Ihs Manufacturer INTEL CORP
Part Package Code DIP
Package Description DIP, DIP24,.3
Clock Frequency-Max 33.3 MHz
Number of I/O Lines 16I/O Lines
Operating Temperature-Max 70 °C
Package Body Material CERAMIC, GLASS-SEALED
Package Code DIP
Package Equivalence Code DIP24,.3
Package Shape RECTANGULAR
Package Style IN-LINE
Supply Voltage-Max 5.25 V
Supply Voltage-Min 4.75 V
Supply Voltage-Nom 5 V
JESD-609 Code e0
Terminal Finish TIN LEAD
Additional Feature PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
HTS Code 8542.39.00.01
Terminal Position DUAL
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Reach Compliance Code compliant
Pin Count 24
JESD-30 Code R-GDIP-T24
Number of Outputs 16Outputs
Qualification Status Not Qualified
Temperature Grade COMMERCIAL
Propagation Delay 25 ns
Architecture PAL-TYPE
Number of Inputs 20Inputs
Organization 4 DEDICATED INPUTS, 16 I/O
Seated Height-Max 5.72 mm
Programmable Logic Type UV PLD
Output Function MACROCELL
Number of Dedicated Inputs 4Dedicated Inputs
Number of Product Terms 160Product Terms
Length 32.07 mm
Width 7.62 mm
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DPLD610-25 Documents

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