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- GAL20V8B-15LP
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GAL20V8B-15LP Tech Specifications
Category | Embedded - CPLDs (Complex Programmable Logic Devices) | |
Manufacturer | Lattice Semiconductor | |
Mount | Through Hole | |
Mounting Type | Through Hole | |
Package / Case | 24-DIP (0.300, 7.62mm) | |
Number of Pins | 24Pins | |
Number of I/Os | 8I/Os | |
Operating Temperature | 0°C~75°C TA | |
Packaging | Tube | |
Series | GAL®20V8 | |
Published | 2000 | |
JESD-609 Code | e0 | |
Pbfree Code | no | |
Part Status | Obsolete | |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) | |
Number of Terminations | 24Terminations | |
ECCN Code | EAR99 | |
Additional Feature | REGISTER PRELOAD; POWER-UP RESET | |
Terminal Position | DUAL | |
Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
Supply Voltage | 5V | |
Terminal Pitch | 2.54mm | |
Reach Compliance Code | not_compliant | |
Frequency | 62.5MHz |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
Base Part Number | GAL20V8 | |
Pin Count | 24 | |
Number of Outputs | 8Outputs | |
Qualification Status | Not Qualified | |
Power Supplies | 5V | |
Programmable Type | EE PLD | |
Max Supply Voltage | 5.25V | |
Min Supply Voltage | 4.75V | |
Operating Supply Current | 75mA | |
Nominal Supply Current | 90mA | |
Propagation Delay | 15 ns | |
Architecture | PAL-TYPE | |
Output Function | MACROCELL | |
Number of Macro Cells | 8Macro Cells | |
Number of Dedicated Inputs | 12Dedicated Inputs | |
Voltage Supply - Internal | 4.75V~5.25V | |
Number of Product Terms | 64Product Terms | |
Length | 31.75mm | |
Height Seated (Max) | 5.334mm | |
Width | 7.62mm | |
RoHS Status | Non-RoHS Compliant | |
Lead Free | Lead Free |
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GAL20V8B-15LP Documents
Download datasheets and manufacturer documentation for GAL20V8B-15LP
- DatasheetsPackage Diagrams GAL20V8
- PCN PackagingAll Dev Pkg Mark Chg 12/Nov/2018
- ConflictMineralStatementLattice-Semiconductor-company-57.pdf
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