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ISPPAC-CLK5620V-01T100C Tech Specifications

Category Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Manufacturer Lattice Semiconductor
Mounting Type Surface Mount
Package / Case 100-LQFP
Surface Mount YES
Frequency(Max) 320MHz
Operating Temperature 0°C~70°C
Packaging Tray
Series ispClock™
Published 2000
JESD-609 Code e0
Pbfree Code no
Part Status Obsolete
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 100Terminations
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Voltage - Supply 3V~3.6V
Terminal Position QUAD
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 240
Number of Functions 1Function
Supply Voltage 3.3V
Terminal Pitch 0.5mm
Reach Compliance Code not_compliant
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number ISPPAC-CLK5620
Output HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
Pin Count 100
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 3.6V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 3V
Number of Circuits 1Circuit
Family 5600
Input HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
Ratio - Input:Output 2:20
Logic IC Type PLL BASED CLOCK DRIVER
PLL Yes with Bypass
Differential - Input:Output Yes/Yes
Divider/Multiplier Yes/No
fmax-Min 320 MHz
Same Edge Skew-Max (tskwd) 0.05 ns
RoHS Status Non-RoHS Compliant
Lead Free Lead Free
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ISPPAC-CLK5620V-01T100C Documents

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ISPPAC-CLK5620V-01T100C brand manufacturers: Lattice Semiconductor Corporation, Elecinsight stock, ISPPAC-CLK5620V-01T100C reference price.Lattice Semiconductor Corporation. ISPPAC-CLK5620V-01T100C parameters, ISPPAC-CLK5620V-01T100C Datasheet PDF and pin diagram description download.You can use the ISPPAC-CLK5620V-01T100C Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers, DSP Datesheet PDF, find ISPPAC-CLK5620V-01T100C pin diagram and circuit diagram and usage method of function,ISPPAC-CLK5620V-01T100C electronics tutorials.You can download from the Elecinsight.