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- LC4256V-75TN100C
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LC4256V-75TN100C Tech Specifications
Category | Embedded - CPLDs (Complex Programmable Logic Devices) | |
Manufacturer | Lattice Semiconductor | |
Factory Lead Time | 8 Weeks | |
Mount | Surface Mount | |
Mounting Type | Surface Mount | |
Package / Case | 100-LQFP | |
Number of Pins | 100Pins | |
Weight | 657.000198mg | |
Memory Types | EEPROM | |
Number of I/Os | 64I/Os | |
Operating Temperature | 0°C~90°C TJ | |
Packaging | Tray | |
Series | ispMACH® 4000V | |
Published | 2000 | |
JESD-609 Code | e3 | |
Pbfree Code | yes | |
Part Status | Active | |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) | |
Number of Terminations | 100Terminations | |
ECCN Code | EAR99 | |
Terminal Finish | Matte Tin (Sn) | |
Additional Feature | YES | |
HTS Code | 8542.39.00.01 | |
Terminal Position | QUAD | |
Terminal Form | GULL WING | |
Peak Reflow Temperature (Cel) | 260 | |
Supply Voltage | 3.3V |
Terminal Pitch | 0.5mm | |
Frequency | 322MHz | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Base Part Number | LC4256 | |
Pin Count | 100 | |
Operating Supply Voltage | 3.3V | |
Programmable Type | In System Programmable | |
Max Supply Voltage | 3.6V | |
Min Supply Voltage | 3V | |
Operating Supply Current | 12.5mA | |
Propagation Delay | 7.5 ns | |
Turn On Delay Time | 7.5 ns | |
Number of Logic Blocks (LABs) | 36Logic Blocks (LABs)s | |
Output Function | MACROCELL | |
Number of Macro Cells | 256Macro Cells | |
JTAG BST | YES | |
Number of Dedicated Inputs | 10Dedicated Inputs | |
Voltage Supply - Internal | 3V~3.6V | |
Number of Logic Elements/Blocks | 16Logic Elements/Blocks | |
Height | 1.4mm | |
Length | 14mm | |
Width | 14mm | |
REACH SVHC | No SVHC | |
Radiation Hardening | No | |
RoHS Status | ROHS3 Compliant | |
Lead Free | Lead Free |
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LC4256V-75TN100C Documents
Download datasheets and manufacturer documentation for LC4256V-75TN100C
- DatasheetsPackage Diagrams ispMACH 4000V,B,C,Z Family
- PCN PackagingAll Dev Pkg Mark Chg 12/Nov/2018
- ConflictMineralStatementLattice-Semiconductor-company-57.pdf
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