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- LFE2M50E-6FN672C
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LFE2M50E-6FN672C Tech Specifications
Category | Embedded - FPGAs (Field Programmable Gate Array) | |
Manufacturer | Lattice Semiconductor | |
Factory Lead Time | 8 Weeks | |
Mount | Surface Mount | |
Mounting Type | Surface Mount | |
Package / Case | 672-BBGA | |
Number of Pins | 672Pins | |
Number of I/Os | 372I/Os | |
Operating Temperature | 0°C~85°C TJ | |
Packaging | Tray | |
Series | ECP2M | |
Published | 2012 | |
JESD-609 Code | e1 | |
Pbfree Code | yes | |
Part Status | Active | |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) | |
Number of Terminations | 672Terminations | |
ECCN Code | EAR99 | |
Terminal Finish | Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5) | |
HTS Code | 8542.39.00.01 | |
Voltage - Supply | 1.14V~1.26V | |
Terminal Position | BOTTOM | |
Terminal Form | BALL | |
Peak Reflow Temperature (Cel) | 250 |
Supply Voltage | 1.2V | |
Terminal Pitch | 1mm | |
Reach Compliance Code | not_compliant | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Base Part Number | LFE2M50 | |
Pin Count | 672 | |
Number of Outputs | 372Outputs | |
Qualification Status | Not Qualified | |
Operating Supply Voltage | 1.2V | |
Memory Size | 531kB | |
RAM Size | 518.4kB | |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
Number of Logic Elements/Cells | 48000Logic Elements/Cells | |
Total RAM Bits | 4246528 | |
Max Frequency | 357MHz | |
Number of LABs/CLBs | 6000LABs/CLBs | |
Combinatorial Delay of a CLB-Max | 0.331 ns | |
Number of Logic Cells | 50000Logic Cells | |
Length | 27mm | |
Height Seated (Max) | 2.6mm | |
Width | 27mm | |
RoHS Status | ROHS3 Compliant | |
Lead Free | Lead Free |
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LFE2M50E-6FN672C Documents
Download datasheets and manufacturer documentation for LFE2M50E-6FN672C
- DatasheetsECP2(M) Family Product Selector Guide ECP2(M) Family Handbook
- PCN Design/SpecificationMultiple Devices Cu Wire 01/Jul/2013
- PCN Assembly/OriginAlternate Assembly/Test Site 14/Apr/2014
- PCN PackagingAll Dev Pkg Mark Chg 12/Nov/2018
- ConflictMineralStatementLattice-Semiconductor-company-57.pdf
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