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Microsemi Corporation M2S010TS-FGG484I System On Chip
64KB BOTTOM 484Terminations
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Min. : 1
Mult. : 1
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M2S010TS-FGG484I Tech Specifications
| Category | Embedded - System On Chip (SoC) | |
| Manufacturer | Microsemi | |
| Factory Lead Time | 10 Weeks | |
| Package / Case | 484-BGA | |
| Surface Mount | YES | |
| Number of I/Os | 233I/Os | |
| Operating Temperature | -40°C~100°C TJ | |
| Packaging | Tray | |
| Series | SmartFusion®2 | |
| Published | 2015 | |
| JESD-609 Code | e3 | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | |
| Number of Terminations | 484Terminations | |
| Terminal Finish | MATTE TIN | |
| HTS Code | 8542.39.00.01 | |
| Terminal Position | BOTTOM | |
| Terminal Form | BALL | |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
| Supply Voltage | 1.2V | |
| Terminal Pitch | 1mm | |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | S-PBGA-B484 | |
| Number of Outputs | 233Outputs | |
| Qualification Status | Not Qualified | |
| Supply Voltage-Max (Vsup) | 1.26V | |
| Power Supplies | 1.2V | |
| Supply Voltage-Min (Vsup) | 1.14V | |
| Speed | 166MHz | |
| RAM Size | 64KB | |
| Core Processor | ARM® Cortex®-M3 | |
| Peripherals | DDR, PCIe, SERDES | |
| Connectivity | CANbus, Ethernet, I2C, SPI, UART/USART, USB | |
| Architecture | MCU, FPGA | |
| Number of Inputs | 233Inputs | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Primary Attributes | FPGA - 10K Logic Modules | |
| Number of Logic Cells | 12084Logic Cells | |
| Flash Size | 256KB | |
| Length | 23mm | |
| Height Seated (Max) | 2.44mm | |
| Width | 23mm | |
| RoHS Status | RoHS Compliant |
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M2S010TS-FGG484I Documents
Download datasheets and manufacturer documentation for M2S010TS-FGG484I
- DatasheetsSmartFusion2 Product Brief IGL002 FPGA,SmartFusion2 Datasheet
- PCN Design/SpecificationMult Devices 14/Aug/2017 SF2/IGLOO2 Improvements 18/Jan/2017
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