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- 74LV541D,118
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74LV541D,118 Tech Specifications
| Category | Logic - Specialty Logic | |
| Manufacturer | Nexperia | |
| ECCN (US) | EAR99 | |
| Logic Family | LV | |
| Number of Elements per Chip | 1 | |
| Number of Channels per Chip | 8Channels per Chips | |
| Number of Inputs per Chip | 8Inputs per Chips | |
| Number of Input Enables per Chip | 0 | |
| Number of Outputs per Chip | 8Outputs per Chips | |
| Number of Output Enables per Chip | 2 Low | |
| Bus Hold | No | |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 60(Typ)@1.2V|20(Typ)@2V|11(Typ)@3.3V|15(Typ)@2.7V | |
| Absolute Propagation Delay Time (ns) | 78 | |
| Process Technology | CMOS | |
| Input Signal Type | Single-Ended | |
| Maximum Low Level Output Current (mA) | 8 | |
| Maximum High Level Output Current (mA) | -8 | |
| Minimum Operating Supply Voltage (V) | 1 | |
| Typical Operating Supply Voltage (V) | 3.3 | |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Tolerant I/Os (V) | 5 Inputs | |
| Maximum Quiescent Current (uA) | 160 | |
| Propagation Delay Test Condition (pF) | 50 | |
| Maximum Power Dissipation (mW) | 500 | |
| Minimum Operating Temperature (°C) | -40 | |
| Maximum Operating Temperature (°C) | 125 | |
| Supplier Package | SO | |
| Mounting | Surface Mount | |
| Package Height | 2.45(Max) | |
| Package Length | 13(Max) | |
| Package Width | 7.6(Max) | |
| PCB changed | 20 | |
| Packaging | Tape and Reel | |
| Part Status | Obsolete | |
| Pin Count | 20 | |
| Output Type | 3-State | |
| Polarity | Non-Inverting | |
| Logic Function | Buffer/Line Driver | |
| RoHS Status | Supplier Unconfirmed |
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74LV541D,118 Documents
Download datasheets and manufacturer documentation for 74LV541D,118
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