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- 74AUP1G02GW-Q100H
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74AUP1G02GW-Q100H Tech Specifications
| Category | Logic - Gates and Inverters | |
| Manufacturer | Nexperia | |
| Factory Lead Time | 4 Weeks | |
| Contact Plating | Tin | |
| Mount | Surface Mount | |
| Mounting Type | Surface Mount | |
| Package / Case | 5-TSSOP, SC-70-5, SOT-353 | |
| Logic Level-High | 1.6V ~ 2V | |
| Logic Level-Low | 0.7V ~ 0.9V | |
| Usage Level | Automotive grade | |
| Operating Temperature | -40°C~125°C | |
| Packaging | Tape & Reel (TR) | |
| Series | Automotive, AEC-Q100, 74AUP | |
| JESD-609 Code | e3 | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) | |
| Number of Terminations | 5Terminations | |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL | |
| Terminal Form | GULL WING | |
| Number of Functions | 1Function | |
| Supply Voltage | 1.1V | |
| Terminal Pitch | 0.65mm | |
| Pin Count | 5 | |
| JESD-30 Code | R-PDSO-G5 | |
| Supply Voltage-Max (Vsup) | 3.6V | |
| Supply Voltage-Min (Vsup) | 0.8V | |
| Number of Circuits | 1Circuit | |
| Propagation Delay | 6.4 ns | |
| Quiescent Current | 500nA | |
| Family | AUP/ULP/V | |
| Logic Function | NOR | |
| Number of Inputs | 2Inputs | |
| Logic Type | NOR Gate | |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF | |
| RoHS Status | ROHS3 Compliant |
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74AUP1G02GW-Q100H Documents
Download datasheets and manufacturer documentation for 74AUP1G02GW-Q100H
- PCN PackagingPack/Label Update 30/Nov/2016 Label Chg 12/Mar/2017
- Datasheets74AUP1G02GW-Q100
- PCN Assembly/OriginAssembly Process/Bond Wire Chg 02/Oct/2016
- RohsStatementNXP-Semiconductors-company-12.pdf
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