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- 74AUP2G02GT,115
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74AUP2G02GT,115 Tech Specifications
| Category | Logic - Gates and Inverters | |
| Manufacturer | Nexperia | |
| Factory Lead Time | 13 Weeks | |
| Mount | Surface Mount | |
| Mounting Type | Surface Mount | |
| Package / Case | 8-XFDFN | |
| Number of Pins | 8Pins | |
| Logic Level-High | 1.6V ~ 2V | |
| Logic Level-Low | 0.7V ~ 0.9V | |
| Operating Temperature | -40°C~125°C | |
| Packaging | Tape & Reel (TR) | |
| Series | 74AUP | |
| Published | 2010 | |
| JESD-609 Code | e4 | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) | |
| Number of Terminations | 8Terminations | |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) | |
| Voltage - Supply | 0.8V~3.6V | |
| Terminal Position | DUAL | |
| Peak Reflow Temperature (Cel) | 260 |
| Number of Functions | 1Function | |
| Supply Voltage | 1.1V | |
| Terminal Pitch | 0.5mm | |
| Time@Peak Reflow Temperature-Max (s) | 30 | |
| Base Part Number | 74AUP2G02 | |
| Pin Count | 8 | |
| Number of Outputs | 1Output | |
| Supply Voltage-Max (Vsup) | 3.6V | |
| Propagation Delay | 6.4 ns | |
| Quiescent Current | 500nA | |
| Turn On Delay Time | 19.9 ns | |
| Family | AUP/ULP/V | |
| Logic Function | NOR | |
| Logic Type | NOR Gate | |
| Number of Gates | 2Gates | |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF | |
| Height Seated (Max) | 0.5mm | |
| Radiation Hardening | No | |
| RoHS Status | ROHS3 Compliant | |
| Lead Free | Lead Free |
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74AUP2G02GT,115 Documents
Download datasheets and manufacturer documentation for 74AUP2G02GT,115
- Datasheets74AUP2G02
- PCN PackagingLabel Chg 12/Mar/2017
- RohsStatementNXP-Semiconductors-company-12.pdf
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