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74LV573PW,112 Tech Specifications

Category Logic - Latches
Manufacturer NXP
Mounting Type Surface Mount
Package / Case 20-TSSOP (0.173, 4.40mm Width)
Surface Mount YES
Operating Temperature -40°C~125°C
Packaging Tube
Series 74LV
Published 2009
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20Terminations
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Additional Feature BROADSIDE VERSION OF 373
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 260
Number of Functions 1Function
Supply Voltage 3.3V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV573
Pin Count 20
JESD-30 Code R-PDSO-G20
Qualification Status Not Qualified
Output Type Tri-State
Circuit 8:8
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Number of Ports 2Ports
Number of Bits 8Bits
Family LV/LV-A/LVX/H
Output Characteristics 3-STATE
Logic Type D-Type Transparent Latch
Output Polarity TRUE
Max I(ol) 0.008 A
Prop. Delay@Nom-Sup 29 ns
Independent Circuits 1
Delay Time - Propagation 24ns
Length 6.5mm
Width 4.4mm
RoHS Status ROHS3 Compliant
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