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HD74LV08AFPEL Tech Specifications
| Category | Logic - Gates and Inverters | |
| Manufacturer | Renesas | |
| Surface Mount | YES | |
| Number of Terminals | 14Terminals | |
| ECCN (US) | EAR99 | |
| Logic Family | LV | |
| Number of Elements per Chip | 4Elements per Chips | |
| Number of Element Inputs | 2-INElement Input | |
| Number of Output Enables per Element | 0 | |
| Number of Selection Inputs per Element | 0 | |
| Number of Element Outputs | 1Element Output | |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 12.3@3.3V|7.9@5V|17.3@2.5V | |
| Absolute Propagation Delay Time (ns) | 20 | |
| Process Technology | CMOS | |
| Maximum Low Level Output Current (mA) | 12 | |
| Maximum High Level Output Current (mA) | -12 | |
| Minimum Operating Supply Voltage (V) | 2 | |
| Typical Operating Supply Voltage (V) | 5|2.5|3.3 | |
| Maximum Operating Supply Voltage (V) | 5.5 | |
| Maximum Quiescent Current (uA) | 20 | |
| Propagation Delay Test Condition (pF) | 50 | |
| Minimum Operating Temperature (°C) | -40 | |
| Maximum Operating Temperature (°C) | 85 | |
| Standard Package Name | SOP | |
| Supplier Package | SOP | |
| Mounting | Surface Mount | |
| Package Height | 2(Max) | |
| Package Length | 10.06 | |
| Package Width | 5.5 | |
| PCB changed | 14 | |
| Lead Shape | Gull-wing | |
| Package Description | SOP-14 | |
| Package Style | SMALL OUTLINE | |
| Load Capacitance (CL) | 50 pF | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Equivalence Code | SOP14,.3 | |
| Operating Temperature-Min | -40 °C | |
| Reflow Temperature-Max (s) | NOT SPECIFIED | |
| Operating Temperature-Max | 85 °C | |
| Rohs Code | No | |
| Manufacturer Part Number | HD74LV08AFPEL |
| Supply Voltage-Nom (Vsup) | 2.5 V | |
| Package Code | SOP | |
| Package Shape | RECTANGULAR | |
| Manufacturer | Renesas Electronics Corporation | |
| Part Life Cycle Code | Active | |
| Ihs Manufacturer | RENESAS ELECTRONICS CORP | |
| Risk Rank | 5.06 | |
| Part Package Code | SOIC | |
| Prop. | 14 ns | |
| Packaging | Tape and Reel | |
| Pbfree Code | Yes | |
| Part Status | Active | |
| HTS Code | 8542.39.00.01 | |
| Subcategory | Gates | |
| Packing Method | TAPE AND REEL | |
| Technology | CMOS | |
| Terminal Position | DUAL | |
| Terminal Form | GULL WING | |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
| Number of Functions | 4Functions | |
| Terminal Pitch | 1.27 mm | |
| Reach Compliance Code | unknown | |
| Pin Count | 14 | |
| JESD-30 Code | R-PDSO-G14 | |
| Qualification Status | Not Qualified | |
| Supply Voltage-Max (Vsup) | 5.5 V | |
| Power Supplies | 3.3 V | |
| Temperature Grade | INDUSTRIAL | |
| Supply Voltage-Min (Vsup) | 2 V | |
| Family | LV/LV-A/LVX/H | |
| Logic Function | AND | |
| Number of Inputs | 2Inputs | |
| Seated Height-Max | 2.2 mm | |
| Logic IC Type | AND GATE | |
| Max I(ol) | 0.006 A | |
| Propagation Delay (tpd) | 20 ns | |
| Schmitt Trigger | NO | |
| Width | 5.5 mm | |
| Length | 10.06 mm | |
| RoHS Status | RoHS non-compliant |
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HD74LV08AFPEL Documents
Download datasheets and manufacturer documentation for HD74LV08AFPEL
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