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- SN74AUP1G125DRLR
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SN74AUP1G125DRLR Tech Specifications
Category | Logic - Buffers, Drivers, Receivers, Transceivers | |
Manufacturer | Texas Instruments | |
Factory Lead Time | 6 Weeks | |
Lifecycle Status | ACTIVE (Last Updated: 4 days ago) | |
Contact Plating | Gold | |
Package / Case | SOT-553 | |
Mounting Type | Surface Mount | |
Mount | Surface Mount | |
Number of Pins | 5Pins | |
Series | 74AUP | |
Packaging | Tape & Reel (TR) | |
Operating Temperature | -40°C~85°C TA | |
JESD-609 Code | e4 | |
Pbfree Code | yes | |
Part Status | Active | |
Moisture Sensitivity Level (MSL) | 1 (Unlimited) | |
Number of Terminations | 5Terminations | |
ECCN Code | EAR99 | |
Packing Method | TR | |
Voltage - Supply | 0.8V~3.6V | |
Terminal Position | DUAL | |
Peak Reflow Temperature (Cel) | 260 | |
Number of Functions | 1Function | |
Supply Voltage | 1.2V | |
Base Part Number | 74AUP1G125 | |
Pin Count | 5 |
Output Type | 3-State | |
Polarity | Non-Inverting | |
Supply Voltage-Max (Vsup) | 3.6V | |
Supply Voltage-Min (Vsup) | 0.8V | |
Number of Channels | 1Channel | |
Load Capacitance | 30pF | |
Number of Ports | 2Ports | |
Number of Bits | 1Bit | |
Propagation Delay | 18.7 ns | |
Quiescent Current | 500nA | |
Turn On Delay Time | 25.5 ns | |
Family | AUP/ULP/V | |
Logic Function | Buffer, Inverting | |
Logic Type | Buffer, Non-Inverting | |
Max I(ol) | 0.004 A | |
Control Type | ENABLE LOW | |
Number of Output Lines | 1Output Line | |
Count Direction | UNIDIRECTIONAL | |
Height | 600μm | |
Width | 1.2mm | |
Length | 1.6mm | |
Thickness | 550μm | |
RoHS Status | ROHS3 Compliant | |
Radiation Hardening | No | |
REACH SVHC | No SVHC | |
Lead Free | Lead Free |
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SN74AUP1G125DRLR Documents
Download datasheets and manufacturer documentation for SN74AUP1G125DRLR
- PCN Design/SpecificationDie Conversion 09/Oct/2014 Die Conversion Revision A 19/Feb/2015
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