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- XCV600-4BGG560I
Xilinx XCV600-4BGG560I FPGA &CPLD Boards
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XCV600-4BGG560I Tech Specifications
| Category | Evaluation Boards - Embedded - Complex Logic (FPGA, CPLD) | |
| Manufacturer | Xilinx | |
| Surface Mount | YES | |
| Number of Terminals | 560Terminals | |
| Manufacturer Part Number | XCV600-4BGG560I | |
| Rohs Code | Yes | |
| Part Life Cycle Code | Obsolete | |
| Ihs Manufacturer | XILINX INC | |
| Part Package Code | BGA | |
| Package Description | LBGA, | |
| Risk Rank | 5.79 | |
| Clock Frequency-Max | 250 MHz | |
| Moisture Sensitivity Levels | 3 | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | LBGA | |
| Package Shape | SQUARE | |
| Package Style | GRID ARRAY, LOW PROFILE | |
| Supply Voltage-Max | 2.625 V | |
| Supply Voltage-Nom | 2.5 V | |
| Reflow Temperature-Max (s) | 30 | |
| Supply Voltage-Min | 2.375 V |
| JESD-609 Code | e1 | |
| Pbfree Code | Yes | |
| ECCN Code | EAR99 | |
| Terminal Finish | Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) | |
| HTS Code | 8542.39.00.01 | |
| Terminal Position | BOTTOM | |
| Terminal Form | BALL | |
| Peak Reflow Temperature (Cel) | 260 | |
| Terminal Pitch | 1.27 mm | |
| Reach Compliance Code | compliant | |
| Pin Count | 560 | |
| JESD-30 Code | S-PBGA-B560 | |
| Qualification Status | Not Qualified | |
| Organization | 3456 CLBS, 661111 GATES | |
| Seated Height-Max | 1.7 mm | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Combinatorial Delay of a CLB-Max | 0.8 ns | |
| Number of CLBs | 3456CLBs | |
| Number of Equivalent Gates | 661111Equivalent Gates | |
| Length | 42.5 mm | |
| Width | 42.5 mm |
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