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- XC2C128-6TQ144C
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XC2C128-6TQ144C Tech Specifications
| Category | Embedded - CPLDs (Complex Programmable Logic Devices) | |
| Manufacturer | Xilinx | |
| Factory Lead Time | 10 Weeks | |
| Mount | Surface Mount | |
| Mounting Type | Surface Mount | |
| Package / Case | 144-LQFP | |
| Number of Pins | 144Pins | |
| Memory Types | ROMless | |
| Number of I/Os | 100I/Os | |
| Operating Temperature | 0°C~70°C TA | |
| Packaging | Tray | |
| Series | CoolRunner II | |
| Published | 2001 | |
| JESD-609 Code | e0 | |
| Pbfree Code | no | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | |
| Number of Terminations | 144Terminations | |
| ECCN Code | EAR99 | |
| Additional Feature | YES | |
| Terminal Position | QUAD | |
| Terminal Form | GULL WING | |
| Peak Reflow Temperature (Cel) | 225 |
| Supply Voltage | 1.8V | |
| Terminal Pitch | 0.5mm | |
| Time@Peak Reflow Temperature-Max (s) | 30 | |
| Base Part Number | XC2C128 | |
| Pin Count | 144 | |
| Qualification Status | Not Qualified | |
| Operating Supply Voltage | 1.8V | |
| Supply Voltage-Max (Vsup) | 1.9V | |
| Programmable Type | In System Programmable | |
| Propagation Delay | 6 ns | |
| Number of Logic Elements/Cells | 8Logic Elements/Cells | |
| Number of Gates | 3000Gates | |
| Max Frequency | 244MHz | |
| Speed Grade | 6 | |
| Output Function | MACROCELL | |
| Number of Macro Cells | 128Macro Cells | |
| JTAG BST | YES | |
| Voltage Supply - Internal | 1.7V~1.9V | |
| Delay Time tpd(1) Max | 5.7ns | |
| Length | 20mm | |
| Width | 20mm | |
| RoHS Status | Non-RoHS Compliant |
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XC2C128-6TQ144C Documents
Download datasheets and manufacturer documentation for XC2C128-6TQ144C
- Design ResourcesCoolRunner-II CPLD Designer Guide
- DatasheetsXC2C128 Datasheet CoolRunner-II CPLD Family
- PCN Design/SpecificationShipping Tray TQ144 and TQG144 12/Aug/2013
- PCN Assembly/OriginMult Dev LeadFrame Chg 29/Oct/2018
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